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Imec Improves Performance, Reliability of Deeply-scaled CMOS Logic Devices

Paves the way to silicon CMOS devices beyond the 5nm technology node.

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By: DAVID SAVASTANO

Contributing Editor, Coatings World and Ink World, Coatings World and Ink World Magazine

At IEEE International Electron Devices Meeting 2015, imec presented results to increase performance and improve reliability of deeply scaled silicon CMOS logic devices.

Continued transistor scaling has resulted in increased transistor performance and transistor densities for the last 50 years. With transistor scaling reaching the critical limits of atomic dimensions, imec’s R&D program on advanced logic scaling targets the new and mounting challenges for performance, power, cost and density scaling to future process technologies.

Imec is looking into extending silicon CMOS technology by tackling the detrimental impact of parasitics on device performance and reliability, and by introducing novel architectures such as gate-all-around nanowires, that are considered to improve short channel control.

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, Panasonic, Qualcomm, Samsung, SK Hynix, Sony and TSMC.

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